Towards High-Performance Supersingular Isogeny Cryptographic Hardware Accelerator Design

Cryptosystems based on supersingular isogeny are a novel tool in post-quantum cryptography. One compelling characteristic is their concise keys and ciphertexts. However, the performance of computation currently worse than that other schemes. This primarily due to following factors. Firstly, underlying field quadratic extension finite field, resulting higher computational complexity. Secondly, strategy for large-degree evaluation complex dependent elementary arithmetic units employed. Thirdly, adapting same hardware different parameters challenging. Considering evolution similar curve-based cryptosystems, we believe proper algorithm optimization acceleration will reduce its speed overhead. paper describes high-performance flexible architecture accelerates computation. Specifically, optimize design by creating dedicated Montgomery multiplier an efficient scheduling suitable isogeny. The operates Fp2 under projective coordinate formulas, tailored it. By exploiting additional parallelism through replicated multipliers concurrent subroutines, our 65 nm SMIC technology cryptographic accelerator can generate ephemeral public 2.40 ms Alice 2.79 Bob with 751-bit prime setting. Sharing secret key costs another 2.04 2.35 ms, respectively.